How long does a track need to be to cause EMC issues?
- Francesco Poderico
- Oct 14
- 3 min read
Today I want to talk about how apparently short PCB tracks can still create big EMC problems—especially when they carry a clock in the 20–30 MHz range.
A very common setup
You’ve got a clock source (XO or MCU clock out) driving something like a USB/Ethernet transceiver or an SPI flash. The driver is low-impedance (≈ 20 Ω), the track length is, say, 25 cm, and the receiver load is around 10–20 pF. Let’s pick a concrete example: 25 MHz clock.
If you only look at the fundamental to estimate wavelength using
λ=fc
you’ll get λ25 MHz≈12 m, and a quarter-wave of 3 m—so a 25 cm track sounds “short” and harmless. Then you go to the EMC lab and… fail at 225 MHz. What happened?
Square waves = lots of harmonics
A 25 MHz square wave isn’t just 25 MHz; it contains strong odd harmonics (3rd, 5th, 7th, 9th, …). So you must consider those frequencies when thinking about radiation.
Let’s list the key ones up to the 9th (that’s where many products still struggle):
Key point: radiation is efficient when the physical structure (track + return path + discontinuities) approaches a fraction of a wavelength (¼, ⅛, etc.). So a 25 cm route can absolutely light up the 7th/9th harmonics—especially if it crosses a plane gap or changes layer without nearby ground vias (poor return = bigger loop = stronger antenna).
Reality check for PCBs: the effective wavelength on a board is shorter than in air (vp≈c/εeff). You don’t need an exact quarter-wave length to radiate—a combination of loop area, return detours, and discontinuities can make even 20–30 cm routes surprisingly loud around 175–225 MHz.
“We failed at 225 MHz—now what?”
First, confirm the radiator. If you have external cables, clip a ferrite on the suspect one; if the 225 MHz peak drops, the cable is acting as the antenna exporting your board’s noise.
Next, relate 225 MHz back to your clocks:
225/9 = 25 MHz ← likely the parent clock (9th harmonic)
225/7 ≈ 32.14 MHz
225/5 = 45 MHz…you get the idea.
If you do have 25 MHz on the board, the 9th is a prime suspect.
Practical fixes (from least invasive to more invasive)
A) Small series resistor at the source10–33 Ω near the driver. This gently slows the edge and reduces high-order harmonic energy (often knocks the 7th/9th down a few dB). Verify timing margins.
B) Tiny shunt capacitor at the source2.2–18 pF NP0/C0G. This low-passes the edge and trims higher harmonics (more effective at very high orders). Watch for added jitter and duty-cycle distortion; only use if your timing budget allows.
C) Nudge the clock up (counterintuitive but powerful)If you’re failing by 3–4 dB around 200–230 MHz, consider raising the base clock so the same harmonic order lands above 230 MHz. In EN 55011 Class B (3 m) the limit jumps from 40 to 47 dBµV/m at 230 MHz—that’s +7 dB of instant headroom.
Example: 25 MHz → 27 MHz moves the 9th from 225 → 243 MHz. Re-scan to confirm; check that interfaces using the clock tolerate the change. (Full explanation is in my previous post.)
“Why can we often ignore ≥11th for 25 MHz in this context?”
Because for EN 55011 Class B (3 m), anything above 230 MHz enjoys +7 dB higher limits. In many real boards the 9th is the loud troublemaker (≤ 230 MHz), while the 11th (275 MHz) ends up past the limit step and is much less likely to fail—so troubleshooting usually focuses on up to the 9th first.
Design guidance (the takeaway)
When you route a clock, try to keep the effective route (including meanders, stubs, and return detours) well below the quarter-wave of the 9th harmonic. If that’s not possible, terminate the line appropriately and/or apply A/B/C above.
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